ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design

URI http://harp.lib.hiroshima-u.ac.jp/hiroshima-cu/metadata/5717
ファイル
タイトル
ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design
著者
氏名 OCHI Hiroyuki
ヨミ オチ ヒロユキ
別名 上土井 陽子
氏名 KAMIDOI Yoko
ヨミ カミドイ ヨウコ
別名 川端 英之
氏名 KAWABATA Hideyuki
ヨミ カワバタ ヒデユキ
別名
キーワード
education of computer architecture
system design
DLX-like pipelined RISC processor
field-programmable gate array
verilog-HDL
抄録

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a <>Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

査読の有無
掲載雑誌名
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
E80-A
10
開始ページ
1826
終了ページ
1833
出版年月日
1997-10-20
出版者
電子情報通信学会(IEICE)
ISSN
0916-8508
NCID
AA10826239
本文言語
英語
資料タイプ
学術雑誌論文
著者版フラグ
出版社版
権利情報
copyright©1997IEICE
関連URL
旧URI
区分
hiroshima-cu