An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
URI | http://harp.lib.hiroshima-u.ac.jp/hiroshima-cu/metadata/6024 | ||||||||||||||||||
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E91-D_3 _713.pdf
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Open Date
:2010-03-18
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Title |
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
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Subject |
test compression
ATE
reconfigurability
variable-length coding
test application
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Abstract |
Test compression / decompression scheme for reducing the test application time and memory requirement of an LSI tester has been proposed. In the scheme, the employed coding algorithms are tailored to a given test data, so that the tailored coding algorithm can highly compress the test data. However, these methods have some drawbacks, e.g., the coding algorithm is ineffective in extra test data except for the given test data. In this paper, we introduce an embedded decompressor that is reconfigurable according to coding algorithms and given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-reconfigurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT. Experimental results show that (1) the configuration data size becomes reasonably small by reducing the configuration part of the decompressor, (2) the reconfigurable decompressor is effective for SoC testing in respect of the test data size, and (3) it can achieve an optimal compression of test data by Huffman coding. |
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Description Peer Reviewed |
有
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Journal Title |
IEICE TRANSACTIONS on Information and Systems
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Volume |
E91-D
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Issue |
3
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Spage |
713
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Epage |
719
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Published Date |
2008-03-01
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Publisher |
電子情報通信学会(IEICE)
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ISSN |
0916-8532
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Language |
eng
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NIIType |
Journal Article
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Text Version |
出版社版
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Rights |
copyright©2008 IEICE
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Set |
hiroshima-cu
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