A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG

URI http://harp.lib.hiroshima-u.ac.jp/hiroshima-cu/metadata/6028
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Title
A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
Author
氏名 ICHIHARA Hideyuki
ヨミ イチハラ ヒデユキ
別名 市原 英行
氏名 INOUE Tomoo
ヨミ イノウエ トモオ
別名 井上 智生
Subject
test generation
acyclic sequential circuits
stuck-at fault
partial scan
multiple fault
Abstract

A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.

Description Peer Reviewed
Journal Title
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Volume
E86-A
Issue
12
Spage
3072
Epage
3078
Published Date
2003-12-01
Publisher
電子情報通信学会(IEICE)
ISSN
0916-8508
Language
jpn
NIIType
Journal Article
Text Version
出版社版
Rights
copyright©2003IEICE
Relation URL
Old URI
Set
hiroshima-cu