A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG

URI http://harp.lib.hiroshima-u.ac.jp/hiroshima-cu/metadata/6028
ファイル
タイトル
A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
著者
氏名 ICHIHARA Hideyuki
ヨミ イチハラ ヒデユキ
別名 市原 英行
氏名 INOUE Tomoo
ヨミ イノウエ トモオ
別名 井上 智生
キーワード
test generation
acyclic sequential circuits
stuck-at fault
partial scan
multiple fault
抄録

A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.

査読の有無
掲載雑誌名
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
E86-A
12
開始ページ
3072
終了ページ
3078
出版年月日
2003-12-01
出版者
電子情報通信学会(IEICE)
ISSN
0916-8508
本文言語
日本語
資料タイプ
学術雑誌論文
著者版フラグ
出版社版
権利情報
copyright©2003IEICE
関連URL
旧URI
区分
hiroshima-cu