Testing for the Programming Circuit of SRAM-Based FPGAs

URI http://harp.lib.hiroshima-u.ac.jp/hiroshima-cu/metadata/6415
File
Title
Testing for the Programming Circuit of SRAM-Based FPGAs
Author
氏名 MICHINISHI Hiroyuki
ヨミ ミチニシ ヒロユキ
別名 井上 智生
氏名 YOKOHIRA Tokumi
ヨミ ヨコヒラ トクミ
別名
氏名 OKAMOTO Takuji
ヨミ オカモト タクジ
別名
氏名 INOUE Tomoo
ヨミ イノウエ トモオ
別名
氏名 FUJIWARA Hideo
ヨミ フジワラ ヒデオ
別名
Subject
fault detection
LUT-based FPGA
SRAM-based FPGA
functional fault
configuration
Abstract

he programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.

Description Peer Reviewed
Journal Title
IEICE TRANSACTIONS on Information and Systems
Volume
E82-D
Issue
6
Spage
1051
Epage
1057
Published Date
1999-06-20
Publisher
電子情報通信学会(IEICE)
ISSN
0916-8532
Language
eng
NIIType
Journal Article
Text Version
出版社版
Rights
copyright©1999 IEICE
Relation URL
Old URI
Set
hiroshima-cu