形式検証とランダムシミュレーションを併用した大規模ハードウェア設計検証
URI | http://harp.lib.hiroshima-u.ac.jp/it-hiroshima/metadata/10457 | ||||||||||||||||||
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ファイル |
035.pdf
( 214.0 KB )
公開日
:2012-09-05
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タイトル |
形式検証とランダムシミュレーションを併用した大規模ハードウェア設計検証
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別タイトル |
Large-scale Hardware Verification by Using Formal Method and Random Simulation Together
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著者 |
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抄録 |
Formal verification is one of automated techniques to guarantee the correctness of hardware designs. The computational cost of formal verification, however, grows larger for a large-scale design, so that we cannot get the solution. In this paper, we propose a method to utilize intermediate data, which formal verification has generated, for a random simulation. Our method aims to avoid spoiling the computational cost for formal verification even if it does not terminate. |
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掲載雑誌名 |
IEEE SMC Hiroshima Chapter Young Researchers' Workshop proceedings : IEEE SMC Hiroshima Chapter若手研究会講演論文集
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巻 |
2012
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開始ページ |
119
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終了ページ |
120
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出版年月日 |
2012-07
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出版者 |
IEEE SMC Hiroshima Chapter
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ISSN |
2187-3577
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NCID |
HP01495586
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NAID |
40019881898
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本文言語 |
日本語
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資料タイプ |
会議発表論文
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著者版フラグ |
著者版
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権利情報 |
©Copyright by IEEE SMC Hiroshima Chapter. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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区分 |
it-hiroshima
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