3次元VLSI設計のための5層チャネルルータの開発

URI http://harp.lib.hiroshima-u.ac.jp/it-hiroshima/metadata/3753
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Title
3次元VLSI設計のための5層チャネルルータの開発
Title Alternative
Development of a 5-layer Channel Router for 3-D VLSI Design
Author
氏名 大村 道郎
ヨミ オオムラ ミチロウ
別名 Ohmura Michiroh
氏名 岡本 好広
ヨミ オカモト ヨシヒロ
別名 Okamoto Yoshihiro
Subject
VLSI
3-D
layout
channel
router
NDC
549.7
Abstract

Channel routing is one of the important problems in VLSI layout design. Many channel routing problems have been researched, and one of them is for multilayer channels in which terminals of different nets exist on a column. This problem cannot be solved by the conventional algorithms, which are designed for multilayer channels in which terminals of the same net exist on a column. It is referred to as the 3-D channel routing problem and any method for this problem is discussed on the design speed. In the research of devices in which circuit elements are integrated in 3-D, small chips have been developed since late 1980's. In the layout design that is necessary to develop large-scale 3-D integrated circuits, development of a high-speed routing method is indispensable. In this paper, a fast 5-layer routing method for 3-D rectangular channels is proposed based on the greedy router and it is extended for 3-D irregular channels. The experimental results to evaluate the proposed method are also shown.

Journal Title
広島工業大学紀要. 研究編
Volume
37
Spage
23
Epage
31
Published Date
2003
Publisher
広島工業大学
ISSN
13469975
NCID
AA11599110
Language
jpn
NIIType
Departmental Bulletin Paper
Text Version
出版社版
Old URI
Set
it-hiroshima