広島工業大学におけるIPを用いたLSI設計教育

URI http://harp.lib.hiroshima-u.ac.jp/it-hiroshima/metadata/3807
ファイル
タイトル
広島工業大学におけるIPを用いたLSI設計教育
別タイトル
On an Education of LSI Design using IP in Hiroshima Institute of Technology
著者
氏名 田中 武
ヨミ タナカ タケシ
別名 Tanaka Takeshi
氏名 大村 道郎
ヨミ オオムラ ミチロウ
別名 Ohmura Michiroh
キーワード
VLSI design
intellectual property
CAD
PLD
FPGA
VHDL
NDC
549.7
抄録

The departments of Electronic and Electrical Engineering of Hiroshima Institute of Technology have been teaching integrated circuit designs and processes of semiconductors since 1989. In Electronic Experiments III, students design the logic circuits using fundamental intellectual property (lP) such as BCD-7 segment decoder, shift register, etc. that are expressed by schematic logic design using Graphic Editor, one of MAX-Plus II applications. Typically, students' design time of BCD-7 segment decoder which consists of logic circuits such as NAND, INV, etc. is about 2-3hours. BCD-7 segment decoder is programmed for the FPGA device and its function is confirmed by using push switches and LED. Almost all the students find it best to design the logic circuits using fundamental IP’s. The IP database for VLSI design has been also developed. This database is used to support lectures such as Freshman Seminar, Digital Computer Engineering, Electrical Experiments II, and Design and Drawing.

掲載雑誌名
広島工業大学研究紀要
35
開始ページ
17
終了ページ
23
出版年月日
2001
出版者
広島工業大学
ISSN
03851672
NCID
AN0021271X
本文言語
日本語
資料タイプ
紀要論文
著者版フラグ
出版社版
旧URI
区分
it-hiroshima