Development of a 5-layer Channel Router for 3-D VLSI Design
Channel routing is one of the important problems in VLSI layout design. Many channel routing problems have been researched, and one of them is for multilayer channels in which terminals of different nets exist on a column. This problem cannot be solved by the conventional algorithms, which are designed for multilayer channels in which terminals of the same net exist on a column. It is referred to as the 3-D channel routing problem and any method for this problem is discussed on the design speed. In the research of devices in which circuit elements are integrated in 3-D, small chips have been developed since late 1980's. In the layout design that is necessary to develop large-scale 3-D integrated circuits, development of a high-speed routing method is indispensable. In this paper, a fast 5-layer routing method for 3-D rectangular channels is proposed based on the greedy router and it is extended for 3-D irregular channels. The experimental results to evaluate the proposed method are also shown.